a. It is available after conversion the output linker file b. It is the binary file c. It is the hexadecimal file d. It is available directly from a linker e. It is the text file
a. Low power performance b. Easy development c. High performance d. Low price e. Autonomous & Intelligent peripherals
a. Available division instructions b. DMA block available c. Available multiplication instructions d. Higher clocking e. Larger number of peripherals
a. POR reset b. Power-on reset c. Brown-out reset d. Windowed watchdog reset e. Watchdog reset
a. It is more difficult to use than the CPU in von Neumann architecture b. It has a simple programming model c. It has a one internal bus d. It has split address and data bus e. It has split instruction and data busses
a. HEX file b. OBJ file c. ASM file d. LST file e. MAP file
a. Dhrystone b. MIPS c. FLOPS d. DMIPS e. CoreMark
a. Performance upto 20 MIPS b. Performance upto 32 MIPS c. High energy efficiency d. Available in 6-pin cases e. Many peripherals available
a. TCXO b. VCXO c. OCXO d. TC-VCXO e. XO
a. PIC10 family b. STM32 family c. ATMega family d. STM8 family e. PIC16 family