Architecture

• 8bit CISC processor
• modified harvard architecture
• 4 banks of 8x8b universal registers
• instructions executed in 1, 2, or 3 instruction clock cycles (12 clock pulses)
• 4kB of internal ROM
• 128B of internal SRAM
• four parallel ports P0..P3
• 1x UART
• Two timers (1 used for UART)
• interrupt systems

There was and update adding flash, no special programming was there but they mada only small improvement in fact

8051 pinout (pictures of DIP and LCC,PLCC)

8051 by analog devices

ADuC 824