a. 2 FLOPS b. 1 CoreMark c. 1 MIPS d. 2 MIPS e. 0.5 MIPS
a. 3 b. 2 c. 4 d. 1 e. 5
a. Jazelle instruction list b. Double precision floating point unit c. DSP instructions d. ARM instruction list e. Single precision floating point unit
a. High performance b. Low power performance c. Low price d. Easy development e. Autonomous & Intelligent peripherals
a. 1960's b. 1980's c. 1990's d. 2000's e. 1970's
a. Avoiding unnecessary stack operations b. Reduction of interrupt latency of a single interrupt c. Making interrupt nesting possible d. Increase in overall CPU performance e. Reduction of time lost for interrupt switching
a. It is used to increase the MCU performance b. It is an instruction memory close to the core c. It works like a cache memory d. It is available in Cortex-M4 core e. It is a data memory close to the core
a. 10 Mb/s b. It is not a problem of the SPI interface c. Depends on the electrical capabilities of the master and slave(s) d. Depends on the PCB design e. 20 Mbaud
a. VCC + 0.5 V b. VDD - 0.5 V c. VEE - 0.5 V d. VCC - 2V e. VSS - 0.5 V
a. It isautomatically advanced to point to the next instruction b. It is a register c. It is a peripheral block d. It is pointing the next instruction to be executed e. It is has to be manually stacked during subrouting calls.