a. 0.5 MIPS b. 2 FLOPS c. 2 MIPS d. 1 MIPS e. 1 CoreMark
a. 8-bit wide data memory bus b. Very short instruction list c. Deep stack d. 8-bit wide address memory bus e. Addressing modes embedded into assembly instructions
a. Because of higher clocking b. Because of DSP instructions c. Because of many execution units d. Because of better peripherals e. Because of TCM memory
a. It is a full-duplex interface b. It is a paralel interface c. It is a serial interface d. It is a simplex interface e. Is a sychronous interface
a. It has a one internal bus b. It has split instruction and data busses c. It has split address and data bus d. It is more difficult to use than the CPU in von Neumann architecture e. It has a simple programming model
a. VEE - 0.5 V b. VCC - 2V c. VDD - 0.5 V d. VCC + 0.5 V e. VSS - 0.5 V
a. That the Cortex-M7 core an be used in security applications b. That two cores are processing the same code c. That the Cortex-M7 core is reliable d. That if the results of two cores are different, the CPU will stop e. That two cores are processing different code
a. External RC oscillator b. Internal RC oscillator c. External Crystal Oscillator d. PLL e. External quartz osciallator
a. One data stream b. Complex programming model c. Used in majority of MCUs d. Simple construction e. Multiple data stream
a. High energy efficiency b. Performance upto 20 MIPS c. Many peripherals available d. Available in 6-pin cases e. Performance upto 32 MIPS